1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device fabrication method for realizing an isolation structure in a memory chip, by means of applying a memory cell region formation to an advanced local oxidation of silicon (LOCOS) process, and a peri region to a general step thereof.
2. Description of Conventional Art
A conventional semiconductor device fabrication method for fabricating a 64 MB dynamic random access memory (DRAM) using an advanced LOCOS technique is illustrated in FIGS. 1A-1 through 1I-2. There will be described the fabrication steps in accordance with the accompanying drawings wherein FIGS. 1A-1, 1B-1, . . . 1I-1 as shown on the left side thereof denote a peri region isolation structure and FIGS. 1A-2, 1B-2, . . . 1I-2 as shown on the right side illustrate a cell region isolation structure respectively.
As shown in FIGS. 1A-1 and 1A-2, the first step is to grow a base oxidation 8 as an insulation film on a substrate 1 which is sectioned into a peri region and a cell region. The peri region defines a substrate portion composed of each of a first conductive well (hereinafter, "P-well") and a second conductive well (hereinafter, "N-well"), and the cell region denotes a substrate portion composed of a P-well.
As shown in FIGS. 1B-1 and 1B-2, the second step is to deposit a first nitride film 9 as a first anti-oxidation film on the base oxidation film 8, and to form a pair of photoresist patterns 4 on active pattern regions of the first nitrate film 9 by a lithographic process.
As shown in FIGS. 1C-1 and 1C-2, the third step is to etch the first nitrate film 9 and the base oxidation film 8 using the photoresist 4 as a mask, to form active patterns composed of the oxidation film 8 and the nitride film 9 on the peri and cell regions of the substrate 1. Afterwards, the remaining photoresist 4 is removed.
As shown in FIGS. 1D-1 and 1D-2, the fourth step is, after removing the photoresist 4 includes the following. In the peri region another photoresist pattern 4' is formed that entirely covers the exposed active pattern formed on the second conductive well 5. Then, highly concentrated first conductive impurities (such as p+impurities) are implanted into the substrate 1 of the peri and cell regions using the photoresist 4' as a mask to form N-field ion-implanted regions 10 (such as p+regions) for serving as first field ion-implanted regions in the first conductive wells 7 of each of the peri and cell regions. The photoresist 4' is then removed.
As shown in FIGS. 1E-1 and 1E-2, the fifth step begins forming another photoresist 4" to entirely cover the exposed active pattern formed on the first conductive well 5. Highly concentrated second conductive impurities (such as n+impurities) are then implanted into the substrate 1 using the photoresist 4" as a mask to form P-field ion-implanted regions 11 (such as n+regions) for serving as first field ion-implanted regions in the second conductive well 5 of the peri region. The photoresist 4" is thereafter removed.
As shown in FIGS. 1F-1 and 1F-2, the sixth step is to perform a LOCOS annealing on the substrate 1 having the active patterns thereon, to deposit a second nitrate thin film 12 as a second anti-oxidation film on the annealed surface, and to form thereon a HLD (high temperature and low pressure dielectric) insulation film 13.
As shown in FIGS. 1G-1 and 1G-2, the seventh step is to form side wall spacers on each side wall of the active patterns and on selected surfaces of the substrate 1. The side wall spacers are formed by dry etching portions of the HLD insulation film 13 and a portion of the second nitride film 12. A silicon dry etching is performed with the side wall spacers and the active patterns acting as masks so that the exposed substrate 1 is etched to a defined depth of up to 500 .ANG.. Beginning with FIG. 1G-1, the first conductive well 7 and the second conductive well 5 will be shown without a step therebetween for convenience' sake.
As shown in FIGS. 1H-1 and 1H-2, the eighth step includes performing a field oxidation in the recesses formed during the seventh step so as to form a field oxidation film 14. The HLD insulation film 13 is removed from the side wall spacers. A field diffusion is then performed that results in an N-field 10' being formed in the P-well 7 in each of the peri and cell regions and a P-field 11' being formed in the N-well 5.
As shown in FIGS. 1I-1 and 1I-2, the ninth step is to remove the first nitrate film 9, the second nitrate film 12, and the base oxidation film 8, thus to complete the semiconductor device isolation structure fabrication.
Consequently, the conventional advanced LOCOS technology is focused on isolating the active regions and the device isolation regions from each other using each of the field oxidation film 14, N-field 10' and P-field 11'. Therefore, when a semiconductor device is manufactured using the advanced LOCOS technique, the field oxidation film 14 tends to be formed steeply at its bird's beak portion so that the active regions are less likely to be intruded into by the field oxidation film 14 and become decreased in size. As a result, the conventional technique remains advantageous for forming memory device regions being densely patterned such as a cell region.
However, the LOCOS technique can induce a double hump phenomenon in which a parasitic transistor initially turns on in active edge regions which will be in contact with gates during the device fabrication. The "double hump phenomenon" is illustrated in IEEE Electron Device Letters, Vol. 14, No. 8, August 1991, pp. 412-414 in the article entitled "The Current-Carrying Corner Inherent to Trench Isolation" and in IEEE Transactions on Electron Devices, Vol. Ed.-32, No. 2, February 1985, pp. 441-445 in the article entitled "Analysis of an Anomalous Subthreshold Current in a Fully Recessed Oxide MOSFET Using a Three-Dimensional Device Simulator." Therefore, the LOCOS technique has a disadvantage in that, because of the current leakage and increased stand-by current occurring in a peri region where memory operating circuits are congregated, the memory device operating characteristics can be adversely affected.